9/7 LIFT Reconfigurable Architecture Implementation for Image Authentication

Considering the information system medical images are the most sensitive and critical types of data. Transferring medical images over the internet requires the use of authentication algorithms that are resistant to attacks. Another aspect is confidentiality for secure storage and transfer of medical images. The proposed study presents an embedding technique to improve the security of medical images. As a part of preprocessing that involves removing the high-frequency components, Gaussian filters are used. To get LL band features CDF9/7 wavelet is employed. In a similar way, for the cover image, the LL band features are obtained. In order to get the 1st level of encryption the technique of alpha blending is used. It combines the LL band features of the secret image and cover images whereas LH, HL, and HH bands are applied to Inverse CDF 9/7. The resulting encrypted image along with the key obtained through LH, HL, and HH bands is transferred. The produced key adds an extra layer of protection, and similarly, the receiver does the reverse action to acquire the original secret image. The PSNR acquired from the suggested technique is compared to PSNR obtained from existing techniques to validate the results. Performance is quantified in terms of PSNR. A Spartan 6 FPGA board is used to synthesize the complete architecture in order to compare hardware consumption

An Efficient Reconfigurable Architecture for Fingerprint Recognition

The fingerprint identification is an efficient biometric technique to authenticate human beings in real-time Big Data Analytics. In this paper, we propose an efficient Finite State Machine (FSM) based reconfigurable architecture for fingerprint recognition. The fingerprint image is resized, and Compound Linear Binary Pattern (CLBP) is applied on fingerprint, followed by histogram to obtain histogram CLBP features. Discrete Wavelet Transform (DWT) Level 2 features are obtained by the same methodology. The novel matching score of CLBP is computed using histogram CLBP features of test image and fingerprint images in the database. Similarly, the DWT matching score is computed using DWT features of test image and fingerprint images in the database. Further, the matching scores of CLBP and DWT are fused with arithmetic equation using improvement factor. The performance parameters such as TSR (Total Success Rate), FAR (False Acceptance Rate), and FRR (False Rejection Rate) are computed using fusion scores with correlation matching technique for FVC2004 DB3 Database. The proposed fusion based VLSI architecture is synthesized on Virtex xc5vlx30T-3 FPGA board using Finite State Machine resulting in optimized parameters

FPGA based efficient Multiplier for Image Processing Applications using Recursive Error Free Mitchell Log Multiplier and KOM Architecture

The Digital Image processing applications like medical imaging, satellite imaging, Biometric trait images etc., rely on multipliers to improve the quality of image. However, existing multiplication techniques introduce errors in the output with consumption of more time, hence error free high speed multipliers has to be designed. In this paper we propose FPGA based Recursive Error Free Mitchell Log Multiplier (REFMLM) for image Filters. The 2x2 error free Mitchell log multiplier is designed with zero error by introducing error correction term is used in higher order Karastuba-Ofman Multiplier (KOM) Architectures. The higher order KOM multipliers is decomposed into number of lower order multipliers using radix 2 till basic multiplier block of order 2x2 which is designed by error free Mitchell log multiplier. The 8x8 REFMLM is tested for Gaussian filter to remove noise in fingerprint image. The Multiplier is synthesized using Spartan 3 FPGA family device XC3S1500-5fg320. It is observed that the performance parameters such as area utilization, speed, error and PSNR are better in the case of proposed architecture compared to existing architecture

FPGA Implementation of Fingerprint Recognition System using Adaptive Threshold Technique

The real time fingerprint biometric system is implemented using FGPA. In this paper, we propose FPGA Implementation of Fingerprint Recognition System using Adaptive Threshold Technique with novel adaptive threshold for each person. The fingerprint images are considered from FVC2004 (DB3_A) and processed to resize fingerprint size to 256x256. The DWT is applied on fingerprint and considered only LL coefficients as features of fingerprint. The Adaptive Threshold value for each person is computed using Deviations between two successive samples of a person, Average Deviation, Standard Deviation and constant. The Adaptive Threshold for test image is computed using Deviations between test images and samples of database, Average Deviation, Standard Deviation and constant. If the Average Threshold of test image is less than Average Threshold of a person then it is considered as match else mismatched. It is observed that the success rate of identifying a person is high in the proposed method compared to existing techniques and also the device utilization in the proposed architecture is less compared to existing architecture

An Adaptive Threshold based FPGA Implementation for Object and Face detection

The moving object and face detection are vital requirement for real time security applications. In this paper, we propose an Adaptive Threshold based FPGA Implementation for Object and Face detection. The input Images and reference Images are preprocessed using Gaussian Filter to smoothen the high frequency components. The 2D-DWT is applied on Gaussian filter outputs and only LL bands are considered for further processing. The modified background with adaptive threshold are used to detect the object with LL band of reference image. The detected object is passed through Gaussian filter to enhance the quality of object. The matching unit is designed to recognize face from standard face database images. It is observed that the performance parameters such as percentage TSR and hardware utilizations are better compared to existing techniques

Efficient FPGA Based Matrix Multiplication Using Mux and Vedic Multiplier

Most of the algorithms which are used in DSP, image and video processing, computer graphics, vision and high performance supercomputing applications require multiplication and matrix operation as the kernel operation. In this paper, we propose Efficient FPGA based matrix multiplication using MUX and Vedic multiplier. The 2x2, 3x2 and 3x3 MUX based multipliers are designed. The basic lower order MUX based multipliers are used to design higher order MxN multipliers with a concept of UrdhvaTiryakbyham Vedic approach. The proposed multiplier is used for image processing applications. It is observed that the device utilization and combinational delay are less in the proposed architecture compared to existing architectures

FPGA IMPLEMENTATION OF MOVING OBJECT AND FACE DETECTION USING ADAPTIVE THRESHOLD

The real time moving object and face detections are used for various security applications. In this paper, we propose FPGA implementation of moving object and face detection with adaptive threshold. The input images are passed through Gaussian filter. The 2D-DWT is applied on Gaussian filter output and considered only LL band for further processing to detect object/face. The modified background subtraction technique is applied on LL bands of input images. The adaptive threshold is computed using LL-band of reference image and object is detected through modified background subtraction. The detected object is passed through Gaussian filter to get final good quality object. The face detection is also identified using matching unit along with object detection unit. The reference image is replaced by face database images in the face detection. It is observed that the performance parameters such as TSR, FRR, FAR and hardware related results are improved compared to existing techniques

Implementation of fingerprint based biometric system using optimized 5/3 DWT architecture and modified CORDIC based FFT

The real-time biometric systems are used to authenticate persons for wide range of security applications. In this paper, we propose implementation of fingerprint-based biometric system using Optimized 5/3 DWT architecture and Modified CORDIC-based Fast Fourier Transform (FFT). The Optimized 2D-DWT architecture is designed using Optimized 1D-DWT architectures, Memory Units and novel Controller Unit which is used to scan rows and columns of an image. The database fingerprint image is applied to the proposed Optimized 2D-DWT architecture to obtain four sub-bands of LL, LH, HL and HH. The efficient architecture of FFT is designed by using Modified CORDIC processor which generates twiddle factor angles of range – using Pre-processing Unit and Comparator Block. Further, the LL sub-band coefficients are applied to the Modified CORDIC based FFT to generate final fingerprint

FPGA implementation of moving object and face detection using adaptive threshold

The real time moving object and face detections are used for various security applications. In this paper, we propose FPGA implementation of moving object and face detection with adaptive threshold. The input images are passed through Gaussian filter. The 2D-DWT is applied on Gaussian filter output and considered only LL band for further processing to detect object/face. The modified background subtraction technique is applied on LL bands of input images. The adaptive threshold is computed using LL-band of reference image and object is detected through modified background subtraction. The detected object is passed through Gaussian filter to get final good quality object. The face detection is also identified using matching unit along with object detection unit. The reference image is replaced by face database images in the face detection. It is observed that the performance parameters such as TSR, FRR, FAR and hardware related results are improved compared to existing techniques